Maximizing ESD design window by optimizing gate bias for cascoded drivers in 45nm and beyond SOI technologies

Electrical Overstress/ Electrostatic Discharge Symposium, 2010, Pages 1-6E.

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mosfetbipolar transistorsdriver circuitssilicon-on-insulatorbjt current handlingMore(10+)

Abstract:

In advanced SOI technologies, the bottom gate voltage plays an important role in achieving the maximum trigger voltage Vt1 of the cascoded drivers. A comparable MOSFET and BJT current handling is needed to ensure maximum Vt1. The minimum and maximum Vt1 window for cascoded driver is shown to range between a single FET Vt1 and twice single...More

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