Predictive full circuit ESD simulation and analysis using extended ESD compact models: Methodology and tool implementation

Electrical Overstress/ Electrostatic Discharge Symposium, 2010, Pages 1-8E.

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cmos integrated circuitscircuit optimisationcircuit simulationelectrostatic dischargefailure analysisMore(11+)

Abstract:

We present a new ESD compact modeling methodology using Verilog-A to enable predictive full circuit ESD simulation along with supporting hardware and failure analysis results. We also present a new ESD tool (ESTEEM) to automate the ESD design simulation and optimization flow for circuit designers. Test results show excellent simulation to...More

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