18Gbps, 50mW reconfigurable multi-mode SHA Hashing accelerator in 45nm CMOS

Rajaraman Ramanarayanan,Sanu Mathew,Farhana Sheikh,Suresh Srinivasan,Amit Agarwal,Steven Hsu,Himanshu Kaul,Mark A Anders,Vasantha Erraguntla,Ram Krishnamurthy

Seville（2010）

引用 14|浏览104

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摘要

A multi-mode Secure Hashing Algorithm (SHA) accelerator is fabricated in 45nm CMOS and occupies 0.0625mm2 with 18Gbps throughput and total power consumption of 50mW. The reconfigurable hardware accelerator computes SHA-1/224/256/384/512 message-digest using unified SHA bit-slices and configurable compression circuits resulting in 40% area reduction and <;3% performance overhead for reconfiguration with 23Gbps peak throughput in SHA-224/256 modes. SHA frequency ranges from 21MHz-1.8GHz across 320mV-1.35V supply voltage range.

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关键词

cmos integrated circuits,cryptography,microprocessor chips,reconfigurable architectures,cmos,area reduction,bit rate 18 gbit/s,frequency 21 mhz to 1.8 ghz,message-digest,microprocessor,multimode secure hashing algorithm accelerator,power 50 mw,reconfigurable hardware accelerator,reconfigurable multimode sha hashing accelerator,size 45 nm,voltage 320 mv to 1.35 v,adders,reconfigurable hardware,registers,secure hash algorithm,hardware,throughput,message digest

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