A 2-Bit, 24 dBm, Millimeter-Wave SOI CMOS Power-DAC Cell for Watt-Level High-Efficiency, Fully Digital m-ary QAM Transmitters

A high-efficiency, large output-power, mm-wave digital transmitter architecture is proposed for high data rate m-ary QAM transmission. Because it operates entirely in digital mode, without any matching networks, it is scalable in frequency up to at least 50 GHz and portable to future generations of CMOS technologies. It consists of n broadband mm-wave IQ power-DAC pairs directly modulated in amplitude and phase by 4 x n independent digital data streams. The output signals combine in free space to form a programmable ASK, BPSK, QPSK, and m-ary QAM mm-wave transmitter. Several proof-of-concept circuits with one DAC cell, and with one and two IQ pairs of DAC cells were fabricated in 45-nm SOI CMOS. Using a series-stacked differential output stage with four cascoded n-MOSFETs driven in saturation by a CMOS-inverter chain, each power-DAC cell demonstrates a 24.3 dBm output power with 21.3% drain efficiency and 14.6% PAE, at 45 GHz directly into 50-Ω loads. The peak drain efficiency is 30% at 22.5 dBm output power and 19.4% PAE. Experiments show 5-Gb/s BPSK, and simultaneous 2-Gb/s BPSK and 2-Gb/s ASK modulation per DAC cell in the 44-48 GHz range. Eye diagrams at 28 Gb/s further demonstrate the broadband operation of the DAC cell and its suitability as a large-swing NRZ modulator driver in fiberoptic links.