Direct downconversion architecture performance in compact pulse-Doppler phased array radar receivers
Silicon Monolithic Integrated Circuits in RF Systems(2013)
摘要
Following the design trend of integrated receivers, the direct downconversion (DD) principle is investigated from radar system-level perspective, but with a strong focus on the analog mechanisms. While most modern radar receivers favor a digital downconversion to avoid I/Q mismatches, they demand discrete realization and larger form factors. Recent advances in digital correction algorithms originating from wireless communications, and the ongoing technology scaling of digital circuitry, allows the DD receiver to be pushed into a higher performance class. With analog and digital parts closely interacting, a receiver on chip can provide spurious-free dynamic range beyond 60 dB, suitable for deployment in phased arrays. By evaluating measurement data from self-designed single receivers and applying adequate digital correction methodology, we give essential metrics and performance results to show the feasibility of DD for phased-array radar applications.
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关键词
doppler radar,phased array radar,radar receivers,analog mechanism,compact pulse doppler phased array radar receiver,digital downconversion,direct downconversion architecture,discrete realization,integrated receiver,wireless communication,i/q imbalance,direct downconversion receiver,image rejection ratio,pulse-doppler radar,spurious-free dynamic range,system-on-chip
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