Selective Epitaxial Bipolar Technology for 25 to 40 Gb/s ICs

T F Meister,Reinhard Stengl,A Felder,H M Rein,L Treitinger

Grenoble（1993）

引用 25|浏览7

暂无评分

摘要

A silicon bipolar technology, which uses Selective Epitaxial Growth (SEG) for the active base and collector regions is described. Key features of the SEG transistor configuration are a quasi self-aligned base/collector structure and an epitaxial base process, which has been integrated into a self-aligned double-poly emitter/base configuration. The high speed capability of the SEG transistor concept has been proven by CML gate delay times of 18 ps. In addition several ICs (2:1 static frequency divider, time division multiplexer, demultiplexer) suited for optical-fibre links and measurement equipment have been fabricated.

查看译文

关键词

bipolar digital integrated circuits,bipolar transistors,current-mode logic,delays,elemental semiconductors,epitaxial growth,optical links,semiconductor growth,silicon,cml gate delay time,ic,seg technology,seg transistor configuration,si,active base-collector region,bit rate 25 gbit/s to 40 gbit/s,epitaxial base process,optical-fibre link-measurement equipment,quasiself-aligned base-collector structure,selective epitaxial bipolar technology,self-aligned double-polyemitter-base configuration,time 18 ps,resistance,capacitance,optical fibre,fabrication,multiplexing,transistors

AI 理解论文

溯源树

样例

生成溯源树，研究论文发展脉络

Chat Paper

正在生成论文摘要