A 40-Gb/s 310-fJ/b Inverter-Based CMOS Optical Receiver Front-End

This paper presents a low-power, 40-Gb/s optical receiver front-end fabricated in a 65-nm CMOS technology. By using inverter-based topology for both the transimpedance amplifier (TIA) and post amplifier (PA), high energy efficiency has been obtained. Cascaded amplifiers with transconductance and transimpedance combinations are utilized to acquire bandwidth of 29.6GHz. A low-dropout voltage regulator is applied to reduce supply noise of single-ended amplifiers. The prototype chip excluding output buffer consumes only 12.4 mW (310 fJ/b) at a 1.2-V single supply and the integrated input referred noise is 9.2μArms.