Enhancement-mode GaN-on-Si MOS-FET using Au-free Si process and its operation in PFC system with high-efficiency

Hironobu Miyamoto,Yasuhiro Okamoto,Hiroshi Kawaguchi,Yoshinao Miura,Makoto Nakamura,Tatsuo Nakayama, Ichiro Masumoto, Shinichi Miyake, Tomohiro Hirai, M Fujita,Takehiro Ueda, K Yamanoguchi, Atsushi Tsuboi

Power Semiconductor Devices & IC's(2015)

引用 11|浏览6
暂无评分
摘要
We have developed an enhancement-mode GaN-on-Si MOS-FET with a thin GaN channel (40nm) on a thick AlGaN back barrier layer (1um), using Au-free 150-mm Si process. The developed device showed a threshold voltage Vt of 1.1 V, an on-resistance Ron of 5.4 mΩcm2 and a breakdown voltage BV of 730 V. The developed E-mode GaN MOS-FETs demonstrated the potential for compact and efficient power electronics. A Power Factor Correction (PFC) circuit using the packaged GaN device (20A, 650V) operated with high efficiency of > 94 % at Pout=300 W, Vout=390 V and fSW=300 kHz.
更多
查看译文
关键词
gan,mosfet,pfc circuit,enhancement-mode
AI 理解论文
溯源树
样例
生成溯源树,研究论文发展脉络
Chat Paper
正在生成论文摘要