Prototype of multi-stacked memory wafers using low-temperature oxide bonding and ultra-fine-dimension copper through-silicon via interconnects

Wei Lin,Johnathan E Faltermeier,Kevin R Winstel,Spyridon Skordas,Troy L Gravesabe,Pooja Batra, Kenneth Herman,John Golz,Toshiaki Kirihata,John J Garant,Alex Hubbard, Kris Cauffman, Theodore Levine,James J Kelly,Deepika Priyadarshini,Brown Peethala,Raghuveer Patlolla, Matthew Shoudy,J Demarest,Jean Wynne,D Canaperi,D Mcherron,Daniel J Berger,S S Iyer

SOI-3D-Subthreshold Microelectronics Technology Unified Conference（2014）

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摘要

Reported for the first time is proof-of-concept multi-stacking of memory wafers based on low-temperature oxide wafer bonding using novel design and integration of two types of ultra-fine-dimension copper TSV interconnects. The combined via-middle (intra-via) and via-last (inter-via) strategy allows for the greatest degree of interconnectivity with the tightest allowable pitches and permits a highly integrated interconnect system across the stack. In combination with the successful metallization of the ultra-fine-dimension TSVs, the present work has shown the viability to extend the perceived TSV technology beyond the ITRS roadmap.

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关键词

copper,integrated circuit interconnections,integrated circuit metallisation,integrated memory circuits,low-temperature techniques,three-dimensional integrated circuits,wafer bonding,itrs roadmap,integrated interconnect system,intervia strategy,intravia strategy,low-temperature oxide wafer bonding,multistacked memory wafer,ultrafine-dimension tsv metallization,ultrafine-dimension copper through-silicon via interconnect,via-last strategy,via-middle strategy,3d,dram,tsv,oxide bonding,wafer stacking

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