A 45nm 48-core IA processor with variation-aware scheduling and optimal core mapping

Saurabh Dighe,S K Gupta,Vivek De,Sriram R Vangal,Nitin Borkar,Shekhar Borkar,Kaushik Roy

VLSI Circuits（2011）

引用 29|浏览97

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摘要

This paper describes energy benefits from variation-aware dynamic voltage frequency scaling (VA-DVFS) schemes & presents measured within-die core-to-core maximum operational frequency (Fmax), leakage & thermal variations for a 45nm 48-core IA processor. On-package voltage regulators (OPVR) supplying 8 independent voltage rails combined with 24 frequency islands enable VA-DVFS to exploit these variations for improved performance or energy efficiency. Measurements with industry standard benchmarks on a real system show that the proposed VA-DVFS & optimal core mapping schemes (VA-L & VA-LV) improve core computation energy by up to 21% & chip energy by up to 14.5% across varying voltage/frequency (V/F) operating points & core counts.

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关键词

microprocessor chips,power aware computing,voltage regulators,ia processor,core computation energy,energy efficiency,on-package voltage regulator,optimal core mapping scheme,size 45 nm,variation-aware dynamic voltage frequency scaling,variation-aware scheduling,voltage rails,within-die core-to-core maximum operational frequency,temperature measurement

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