A direct sampling multi-channel receiver for DOCSIS 3.0 in 65nm CMOS

Erwin Janssen,Kostas Doris,A Zanikopoulos,G Van Der Weide,Maarten Vertregt,Olivier Jamin, F Courtois, N Blard, M Kristen

VLSI Circuits（2011）

引用 27|浏览4

暂无评分

摘要

This paper presents a fully integrated direct sampling receiver for DOCSIS 3.0, consisting of a time-interleaved ADC, a digital multi-channel selection filter, and a PLL. The receiver can simultaneously receive 4 streams from arbitrary RF frequencies between 48 and 1002MHz and output these in a 13.5MS/s digital IQ format or at a low-IF through integrated DACs. It consumes 980mW from a split 1.2/1.3/1.6V supply when receiving 4 channels and occupies 16.8mm2 in 65nm CMOS.

查看译文

关键词

cmos integrated circuits,analogue-digital conversion,cable television,phase locked loops,cmos,docsis 3.0,pll,digital multichannel selection filter,direct sampling multichannel receiver,power 980 mw,size 65 nm,time-interleaved adc

AI 理解论文

溯源树

样例

生成溯源树，研究论文发展脉络

Chat Paper

正在生成论文摘要