A highly manufacturable integration technology of 20nm generation 64Gb multi-level NAND flash memory

K W Lee,S K Choi,S J Chung, H L Lee,Su Min Yi, Byeong Il Han, B I Lee, D H Lee, J H Seo,N Y Park,Tae Un Youn,Keum Hwan Noh,M K Lee,J Y Lee,K H Han, Won Sic Woo, S W Cho,S S Kim, Chan Sun Hyun, Weon Joon Suh, Myung Kyu Ahn,H S Kim,K S Kim, G S Cho,S K Park,Seiichi Aritome,J W Kim,S K Lee, S J Hong

VLSI Technology（2011）

引用 28|浏览16

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摘要

Multi-level NAND flash memories with a 20nm design rule have been successfully developed for the first time. A 20nm rule wordline (WL) and bitline (BL) direction have been realized by Spacer Patterning Technology (SPT) of ArF immersion lithography. Key integration technologies include WL airgap with separate gate etch process and optimized control gate (CG) poly deposition process. In addition, many physical and electrical challenges are successfully demonstrated to overcome scaling limit of 20nm technology.

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关键词

nand circuits,flash memories,integrated circuit manufacture,bitline direction,design rule,gate etch process,highly manufacturable integration technology,immersion lithography,multilevel nand flash memory,optimized control gate polydeposition process,rule wordline airgap,size 20 nm,spacer patterning technology,electric fields,interference,capacitance,logic gates,logic gate,electric field

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