A low power preamplifier latch based comparator using 180nm CMOS technology

Design of high speed low power comparators are required to build an efficient analog to digital converters (ADCs). This paper mainly focuses on the preamplifier positive feedback latch based comparator for Asynchronous Successive Approximation Register ADC (ASAR ADC). The main components of such comparator are the preamplifier and latch circuit. Preamplifier is used for removing the kickback noise and the dc offset voltage while the latch is required for the comparison. The proposed architecture operates on three phases which are non overlapping and dissipates 70μWpower when operated on a single 1V supply voltage. The latch is basically a back to back connected inverter circuit which is activated only during the second phase. This specialty credits to the least power dissipation in the circuitry which was designed in 180nm CMOS technology.