Power-efficient CMOS image acquisition system based on compressive sampling
Circuits and Systems（2013）
摘要
A novel compressive sampling scheme suitable for highly scalable hardware implementations is presented. The prototype design is implemented in a 0.18μm standard CMOS technology and utilizes compressed acquisition to boost the overall power efficiency. Specialized pixels, convenient for Comparator-Based Switched Capacitor readout are developed for this purpose. A custom measurement matrix generation algorithm is implemented which reduces in-pixel hardware complexity and performs measurement matrix generation in a single clock cycle. Column-Parallel Differential Cyclic-ADCs based on the Zero-Crossing Detection (ZCD) technique are used to convert the analog image measurements. Physical IC design issues such as the device noise, mismatch and non-linearity, are analyzed and their effects on compressed image acquisition are discussed. The final simulation results show that the proposed 256×256 pixels architecture consumes 1.45mW at 250fps and 26.2mW at 8000fps. The architecture can easily be scaled towards newer technology nodes and higher image resolutions.
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关键词
cmos image sensors,analogue-digital conversion,comparators (circuits),compressed sensing,integrated circuit design,switched capacitor networks,cmos image acquisition system,cmos image sensor,zcd technique,analog image measurements,column-parallel differential cyclic-adcs,comparator-based switched capacitor readout,compressed acquisition,compressed image acquisition,compressive sampling,custom measurement matrix generation algorithm,device noise,in-pixel hardware complexity reduction,physical ic design,power 1.45 mw,power 26.2 mw,power efficiency,prototype design,single clock cycle,size 0.18 mum,specialized pixels,zero-crossing detection technique,cyclic adc,high frame rate,image acquisition,low-power
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