Design and optimization of silicon JFET in 180nm RF/BiCMOS technology

in this paper, we discuss a method to extrapolate intrinsic and extrinsic R-on components for a JFET. The results provide the guideline to lower R-on, hence to achieve competitive "R-on vs. pinch off (V-off)" benchmark. The optimization impacts on channel length scaling and process variation are discussed. Besides, an improved RESURF condition is achieved using one of the experimental conditions. The optimized JFET demonstrates the 50% lowered R-on, low V-off of -2.75V, and high BVdss of 11 V.