An ESD design automation framework and tool flow for nano-scale CMOS technologies
Electrical Overstress/ Electrostatic Discharge Symposium, 2010, Pages 1-6E.
We present a successfully implemented ESD design automation framework that evaluates and verifies the ESD protection methodology at all stages of a standard integrated circuit design flow. The tools used at each step of the flow and sample results showing excellent correlation to hardware test data is presented.
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