A 6b 10GS/s TI-SAR ADC with embedded 2-tap FFE/1-tap DFE in 65nm CMOS

Ehsan Zhian Tabasy,Ayman Shafik,Keytaek Lee,Sebastian Hoyos,Samuel Palermo

VLSI Circuits（2013）

引用 31|浏览8

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摘要

A 64-way time-interleaved successive approximation based ADC front-end efficiently incorporates a 2-tap embedded FFE and a 1-tap embedded DFE, while achieving 4.56-bits peak ENOB at a 10GS/s sampling rate. Fabricated in 1.1V 65nm CMOS, the ADC with embedded equalization achieves 0.48 pJ/conv.-step FOM, while consuming 79.1mW and occupying 0.33mm2 core ADC area.

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关键词

cmos integrated circuits,analogue-digital conversion,adc front end,embedded dfe,embedded equalization,power 79.1 mw,size 65 nm,successive approximation register,time interleaved successive approximation,voltage 1.1 v,adc,adc-based receiver,dfe,ffe,sar,time interleaving,capacitors,calibration

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