A Quick-Turn 3D Structured ASIC Platform for Cost-Sensitive Applications

John Teifel,Richard S. Flores,Robert Jarecki,Todd Bauer,Subhash L. Shinde

2013 IEEE 63RD ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC)（2013）

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Key words

application specific integrated circuits,integrated circuit design,integrated circuit interconnections,three-dimensional integrated circuits,2D metal-via mask,3D die stacks,3D integration technologies,3D structured ASIC platform,fixed vertical interconnect pattern,front-end-of-line TSV,size 0.35 mum,through silicon via

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