Reliability Characterization Of Chip-On-Wafer-On-Substrate (Cowos) 3d Ic Integration Technology

With the size of transistors scaling down, 3D IC packaging emerged as one of the most promising solutions to achieve system integration on the track of Moore's Law. In this article, we demonstrated a sub-system with one 28nm logic device and two 40nm chips on a 600mm(2) silicon interposer with Through-Silicon-Via (TSV) integrating 4 layers of high density interconnects. The packages were assembled using our proprietary CoWoS (Chip on Wafer on Substrate) technology that incorporated 270,000 micro-bump (mu Bump) and 8,700 C4 bumps.Comprehensive reliability characterization and test methods will be presented. It includes copper interconnect reliability of silicon interposer on EM, SM and IMD TDDB with the presence of TSV. mu Bump EM and TSV EM are characterized to provide a design guideline for maximum current carrying capability; the EM test methodology was also used to optimize the integrated process, e.g. TSV copper plating, mu Bump joint, and interface treatment of TSV revealing. Package process optimization, bill of material selection and qualification were conducted on a 28nm Cu/ELK (Extreme low-K) test vehicle taking Chip-Package-Interaction into consideration. Not only component level package reliability tests were performed, board level Thermal Cycling, Power Cycling and Mechanical Shock tests were also executed to understand the reliability margin and potential failure modes in field use condition. The typical failure modes and mechanisms will be discussed. CoWoS technology is eventually successfully developed with enhanced reliability. The results highlight the importance of a highly integrated 3D IC technology from silicon wafer process to assembly packaging. This work shows that in the new paradigm of 3D IC integration, Si Foundry is positioned at a unique leadership to manage the innovation in Si processes and the improvement of Si assembly operating life.