0.5V image processor with 563 GOPS/W SIMD and 32bit CPU using high voltage clock distribution (HVCD) and adaptive frequency scaling (AFS) with 40nm CMOS

Masayasu Nomura,Atsushi Muramatsu, H Takeno, Shinichi Hattori, D Ogawa, M Nasu,K Hirairi,Shigetaka Kumashiro, Shigenori Moriwaki, Yoshiki Yamamoto,Shinji Miyano, Y Hiraku,Izumi Hayashi,Kazuaki Yoshioka,Akira Shikata,Hiroki Ishikuro, Minsik Ahn,Yasuyuki Okuma,Xiaobing Zhang,Yoshikatsu Ryu,Koichi Ishida,Makoto Takamiya,Tadahiro Kuroda,Harumichi Shinohara,Takayasu Sakurai

VLSI Circuits（2013）

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摘要

A 0.5V, 10MHz, 9mW image processor with 320 processing element (PE) SIMD and a 32bit CPU has been developed using 40-nm CMOS. High voltage clock distribution (HVCD) reduces the number of excessive hold buffers required in a 0.5-V logic circuit design, thereby reducing the area, delay, and energy of the SIMD by 14 %, 13%, and 6%, respectively. The 0.5-V SIMD with HVCD achieves an energy efficiency of 563 GOPS/W (= 4.26mW at 7.5MHz), the highest yet reported for near-threshold SIMD. In addition, adaptive frequency scaling (AFS), used to mitigate the impact of the ripple of a buck converters, increases average clock frequency by 33%.

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关键词

logic circuit design,parallel processing,cmos integrated circuits,logic circuits,word length 32 bit,power convertors,hvcd,cmos,pe simd,image processing,high voltage clock distribution,microprocessor chips,processing element,hold buffers,voltage 0.5 v,size 40 nm,power 9 mw,image processor,buck converters,near-threshold simd,digital signal processing chips,cmos technology,logic design,frequency 7.5 mhz,cpu,buffer circuits,frequency 10 mhz,simd,clock distribution networks,afs,power 4.26 mw,ripple,buck converter,adaptive frequency scaling

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