Area-efficient embedded RRAM macros with sub-5ns random-read-access-time using logic-process parasitic-BJT-switch (0T1R) Cell and read-disturb-free temperature-aware current-mode read scheme

Mengfan Chang,Chiacheng Kuo,Shyhshyuan Sheu,Chorngjung Lin,Yachin King,Zhehui Lin,Kengli Su,Yusheng Chen,Wenpin Lin,Hengyuan Lee,Chenhan Tsai,Weisu Chen,Frederick T Chen,Tzukun Ku,Mingjer Kao,Mingjinn Tsai,Juijen Wu,Yuder Chih,Sreedhar Natarajan

VLSI Technology（2013）

引用 19|浏览0

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摘要

Resistive RAM (RRAM) faces two major design challenges: 1) cell area versus write current requirements; 2) cell current (ICELL) versus read disturbance. An RRAM using logic-process-based vertical parasitic-BJT (VPBJT) switches and correspondent cell array (VPBJT-CA) can achieve 4.5+x smaller macro area. To overcome temperature-dependent fluctuation in the base-emitter voltage difference (VBE) of BJT, this work proposes a thermal-aware bitline (BL) voltage bias (VBL-R) scheme (TABB) for current-mode read with 4.7x larger ICELL, and a 1.6x faster read speed. Fabricated 0.18um 1Mb and 65nm 2Mb VPBJT RRAM macros confirm the efficacy of the temperature-aware VBL-R, resulting in the fastest (sub-5ns) random read speed among reported Mb-scaled NVM macros.

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关键词

bipolar transistors,random-access storage,vbl-r scheme,vpbjt switches,area-efficient embedded rram macros,base-emitter voltage difference,cell current,correspondent cell array,current-mode read scheme,logic-process parasitic-bjt-switch,random-read-access-time,read-disturb-free temperature,resistive ram,size 0.18 micron,size 65 nm,temperature-dependent fluctuation,thermal-aware bitline voltage bias,vertical parasitic-bjt,logic design,temperature measurement,fluctuations

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