A DPLL-based per core variable frequency clock generator for an eight-core POWER7 ™ microprocessor

Jose A Tierno,Alexander V Rylyakov,Daniel J Friedman, Ann Chen, Anthony Ciesla,Timothy Diemoz,George English,David Hui,Keith A Jenkins,Paul D Muench, Gaurav Rao,George Smith,Michael Sperling,Kevin Stawiasz

VLSI Circuits（2010）

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摘要

A per-core clock generator for the eight-core POWER7 (TM) processor is implemented with a digital PLL. This frequency generator is capable of smooth, controlled frequency slewing, minimizing the impact of di/dt. Frequency can be dynamically adjusted while the clock is running, and without skipping any cycles, thus enabling aggressive power management techniques.

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关键词

frequency control,generators,time frequency analysis,frequency generator

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