RF and linear performance of commercial 200 mm trap-rich HR-SOI wafers for SoC applications

Cesar Roda Neve,K Ben Alia,C Malaquin,F Allibert,Eric Desbonnets,Isabelle Bertrand,W Van Den Daele,J P Raskin

Silicon Monolithic Integrated Circuits in RF Systems（2013）

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摘要

We present for the first time the RF and linear performance of commercial 200 mm trap-rich HR-SOI wafers. These wafers are fully compatible with the thermal budget of CMOS process. The investigated SOI wafers with a fixed BOX of 400 nm-thick show effective resistivity values higher than 4 kΩ-cm and harmonic distortion levels lower than -81 dBm for a 900 MHz input signal with +15 dBm, i.e. more than 95 dBc. Our investigations confirm the capability of trap-rich HR-SOI wafer for the integration of RF systems in Si.

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关键词

cmos integrated circuits,elemental semiconductors,harmonic distortion,integrated circuit modelling,silicon,silicon-on-insulator,system-on-chip,cmos process,soc,fixed box,frequency 900 mhz,high resistivity silicon-on-insulator,size 200 nm,size 400 nm,thermal budget,trap-rich hr-soi wafers,hr soi,rf integration,tr soi,substrate non-linearity,trap-rich hr soi,trap-rich layer,system on chip,silicon on insulator

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