Embedded Wafer Level Ball Grid Array (eWLB)

The main challenges of today's device packaging are miniaturization, continuously increasing operating frequencies/high data rates, high number of I/Os, reliability, and thermal requirements. One of the major package trends driven by mobile-phone applications is the Wafer Level Ball Grid Array (WLB). Drivers for the implementation of WLB technology are cost reduction, smaller form factor and better electrical performance with respect to high frequency applications. Thin-film WLB technology consists in realizing additional redistribution layers above the passivation of a semiconductor chip using standard thin-film techniques to rearrange peripheral pads on the wafer in an array pattern. A hard limit will be reached with this technology, when the number of I/Os reaches a larger number dian can be fitted on the silicon chip at a given pitch. We introduce Infineon's embedded Wafer Level Ball Grid Array technology, which allows fitting interconnects onto a so-called fan-out area extending the chip area. The core process of this emerging technology is the encapsulation of silicon dice by compression molding. The eWLB technology is a forward-looking development of the WLB technology, upholding the known benefits such as small package dimensions, excellent electrical and thermal performance, and maximum connection density. However, this technology significantly increases the functionality and application spread. Due to eWLB. complex semiconductor chips such as modem and processor chips for applications in mobile communications require a high number of solder connections with standardized contact spacing to be produced with a minimal footprint. At the same time, the packages can be provided with as many solder contacts as needed. The possibility of additional wiring area around the chip proper means that the wafer-level packaging technology also lends itself to new. space-sensitive applications. We demonstrate the capabilities of Infineon's molded embedded Wafer Level Pac- - kage Technology and show how we extended it towards a Platform Technology. The qualified Platform we introduce here covers currently a range of package sizes up to 8×8mm2 at a ball pitch of 0.5mm. The Qualification Criteria we have applied follow the tests described in JEDEC Standard Number 26-A.