A 22nm Soc Platform Technology Featuring 3-D Tri-Gate and High-K/Metal Gate, Optimized for Ultra Low Power, High Performance and High Density Soc Applications
2012 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM)（2012）
Key words
SRAM chips,high-k dielectric thin films,integrated circuit interconnections,low-power electronics,system-on-chip,3D trigate transistor technology,NMOS-PMOS,RF-mixed-signal features,embedded products,frequency 2.6 GHz,handheld products,high density SoC applications,high speed logic transistors,high voltage transistors,high-density interconnect stacks,high-k-metal gate,industry leading drive currents,low standby power,low standby power SRAM,mix-and-match flexibility,mobile products,record low leakage levels,short channel control,size 22 nm,standby leakages,subthreshold slope,transistor types,ultra low power applications,voltage 0.75 V,wireless products
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