A Back - Biased 0.65 μm Leffn CMOS EEPROM Technology For Next - Generation Sub 7 ns Programmable Logic Devices

Michael J. Hart,Philip J. Cacharelis,Roger D. Carpenter,David G. Tsuei,Raminda U. Madurawe,Bal S. Sandhu,Richard G. Smolen,Andrew P. Dumlao,Tim L. Garverick,Thomas McFarlane,Martin H. Manley

Montreux, Switzerland（1991）

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摘要

A high-speed back-biased CMOS EEPROM technology and its application to Programmable Logic Devices (PLDs) will be described. Several key features have allowed the fabrication of a next generation high performance EECMOS PLD; the use of two independent families of transistors for the high voltage programming and read paths, the application of back-bias and careful optimisation of a double-polysilicon EEPROM cell. A sub 7 ns EECMOS PLD is described.

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关键词

programmable logic devices,testing,transistors,cmos technology,low voltage,high voltage,programmable logic device,logic gates,cmos integrated circuits,microelectronics,fabrication,eprom

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