CDM failure modes in a 130nm ASIC technology
Grapevine, TX（2004）
摘要
CDM failures in I/O cells in a 130 nm CMOS ASIC technology are studied. Most failures occurred in internal circuits that were not connected to chip pads. The failures correlate to the I/O power supply network resistance at the I/O cells. Failure modes include gate oxide ruptures on internal nodes driven by active circuits.
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关键词
cmos integrated circuits,application specific integrated circuits,failure analysis,asic technology,cdm failure modes,i/o cells,i/o power supply network resistance,active circuits,chip pads,gate oxide ruptures,size 130 nm,chip,logic gates,electrostatic discharge,resistance,failure mode,metals
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