Development of ultra-thin Chip-on-Wafer process using bumpless interconnects for three-dimensional memory/logic applications

N Maeda,Hitoshi Kitada,Kazushi Fujimoto,Young Soo Kim, S Kodama,S Yoshimi,Masamichi Akazawa,Yoshihiko Mizushima,T Ohba

VLSI Technology（2012）

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摘要

Chip-on-Wafer (COW) stacking structure using stack-first and bumpless interconnects was successfully fabricated for the first time. Chips were arrayed and bonded onto the wafer by back-to-face and gap filling between chips were carried out using organic material without void formation. Chips on the wafer were thinned down to 5 μm. Via-holes were formed at off-chip area (outside the chip). Copper redistribution line was formed using the via-first Damascene method. Lower leakage current as low as back ground was found between pads. No failure and an approximate 100% yield were achieved in the vertical wiring for multi-chips COW stacking.

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关键词

integrated circuit interconnections,leakage currents,logic circuits,storage management chips,three-dimensional integrated circuits,bumpless interconnects,copper redistribution line,leakage current,logic circuit,multichip cow stacking structure,organic material,size 5 mum,stack-first interconnects,three-dimensional memory circuit,ultrathin chip-on-wafer process,vertical wiring,via-first damascene method,3d-ic,bumpless contact and off-chip via,cow,silicon,3d ic,stacking,organic materials

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