A middle-1X nm NAND flash memory cell (M1X-NAND) with highly manufacturable integration technologies

Joowon Hwang,Jihyun Seo,Youngbok Lee, Jongsoon Leem,Jaeseok Kim, Tackseung Hong,Seokho Jeong, Kyeongbock Lee,Hyeeun Heo, Heeyoul Lee,Philsoon Jang,Kyounghwan Park,Myungshik Lee, S J Baik, Hyungoo Kkang, Minsik Jang,Gyuseog Cho,Juyeab Lee,Byungseok Lee,Heehyun Jang,Seokkiu Lee,Seiichi Aritome,S Hong,Sungwook Park

Electron Devices Meeting（2011）

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摘要

A middle-1x nm design rule multi-level NAND flash memory cell (M1X-NAND) has been successfully developed for the first time. 1) QSPT (Quad Spacer Patterning Technology) of ArF immersion lithography is used for patterning mid-1x nm rule wordline (WL). In order to achieve high performance and reliability, several integration technologies are adopted, such as 2) advanced WL air-gap process, 3) floating gate slimming process, and 4) optimized junction formation scheme. And also, by using 5) new N±1 WL Vpass scheme during programming, charge loss and program speed are greatly improved. As a result, mid-1x nm design rule NAND flash memories has been successfully realized.

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关键词

circuit optimisation,flash memories,immersion lithography,integrated circuit interconnections,integrated circuit layout,integrated circuit reliability,nanoelectronics,nanopatterning,m1x-nand,qspt,wl air-gap process,charge loss,floating gate slimming process,mid-1x nm rule wordline patterning,middle-1x nm design rule multilevel nand flash memory cell,optimized junction formation scheme,program speed,quad spacer patterning technology,design rules

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