Gate length scaling and high drive currents enabled for high performance SOI technology using high-κ/metal gate

San Francisco, CA(2008)

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摘要
CMOS devices with high-k/metal gate stacks have been fabricated using a gate-first process flow and conventional stressors at gate lengths of 25 nm, highlighting the scalability of this approach for high performance SOI CMOS technology. AC drive currents of 1630muA/mum and 1190muA/mum have been demonstrated in 45 nm ground-rules at 1V and 200nA/mum off current for nFETs and pFETs, at a Tinv of 14 and 15 respectively. The drive currents were achieved using a simplified high-k/metal gate integration scheme with embedded SiGe and dual stress liners (DSL) and without utilizing additional stress enhancers. Devices have been fabricated with Tinv's down to 12 and 10.5 demonstrating the scalability of this approach for 32 nm and beyond.
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关键词
cmos integrated circuits,field effect transistors,silicon-on-insulator,ac drive currents,cmos devices,dual stress liners,gate length scaling,gate-first process flow,high drive currents,high performance soi cmos technology,high performance soi technology,high-k/metal gate stacks,length scale,cmos technology,metals,dielectrics,silicon on insulator,capacitance,logic gates
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