ESD protection using grounded gate, gate non-silicided (GG-GNS) ESD NFETs in 45nm SOI technology

Sanjit K Mitra,Robert C Gauthier,Junjun Li,Michel J Aboukhalil,Christopher S Putnam,R Halbach,Christopher Seguin

Tucson, AZ（2008）

引用 23|浏览24

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摘要

A non-self protection ESD scheme using grounded-gate, gate non-silicided (GG-GNS) drain/source silicide blocked (SBLK) ESD NFET offered in 45 nm SOI CMOS technology is presented based on a comprehensive study using the high current pulse characteristics. The results show that with a minimum SBLK width over drain/source, GG-GNS NFET can handle ~3.4 mA/mum current.

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关键词

cmos integrated circuits,electrostatic discharge,integrated circuit testing,silicon-on-insulator,cmos technology,drain/source silicide blocked nfet,electrostaitc discharge protection,electrostatic discharge protection,grounded-gate,logic gates,probability density function,resistance,data mining,silicon on insulator

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