Chip-package-board co-design - a DDR3 system design example from circuit designers’ perspective

If package and board level parasitic models are not correctly included, as in many conventional design flows, the simulation results could be too optimistic as the impact from power and signal integrity (PI/SI) is underestimated. In addition, the process and temperature variations could further decrease design margins. In this paper, a detailed chip-package-board (CPB) parasitic model is applied at different process and temperature corners to investigate how PI/SI impacts input/output (I/O) performance of a 1.6-Gbps DDR3 memory system with the supply voltage at 1.5 V, where eye-opening (heye) is the major performance index number. The simulation results indicate that heye may differ as high as 58% if CPB parasitics are not properly modelled, where the issues would be more significant as I/O data rate increases to multi-gigabit-per-second.