SMT and enhanced SPT with recessed SD to improve CMOS device performance

S Fang,Shyue Seng Tan,Jing Yuan,Q Liang,T Dyer, Ron Robinson, Jie Liu,Jae Joon Kim, Bingfeng Zuo,Michael P Belyansky, Jianbing Yan,Zhijiong Luo, Ji Li,Y Wang,Brian J Greene,Huckhui Ng,Yang Li,Huiling Shang, E Maciejewski,M Yang,R Divakaruni,Effendi Leobandung,J Jagannathan

Beijing（2008）

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摘要

For nFET, mechanism of stress memorization technique (SMT) has been investigated. It showed, for the first time, that SMT effect on nFET improvement is not only from poly gate, but also from Si at extension area. For pFET, a novel low cost technique to improve device performance by enhanced stress proximity technique (eSPT) with Recessed SD (ReSD) has been demonstrated for the first time. pFET performance improvement of 40% was demonstrated with eSPT. 15% improvement in ring delay has been demonstrated with optimized eSPT.

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关键词

cmos integrated circuits,field effect transistors,semiconductor devices,stress effects,cmos device performance,nfet,poly gate,recessed sd,ring delay,stress memorization technique,stress proximity technique

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