High-Performance and Low-Power Bulk Logic Platform Utilizing FET Specific Multiple-Stressors with Highly Enhanced Strain and Full-Porous Low-k Interconnects for 45-nm CMOS Technology

Teruo Miyashita,Ken Ikeda,Young Soo Kim,Teruyasu Yamamoto, Y Sambonsugi,Hideaki Ochimizu,Tsunehisa Sakoda,Masaki Okuno,Hiroshi Minakata,Hisashi Ohta,Y Hayami,Katsuaki Ookoshi,Yosuke Shimamune,M Fukuda,A Hatada, Kazuhiro Okabe,Mitsugu Tajima, E Motoh,Tetsu Owada, Mitsuhiro Nakamura,Hiroyuki Kudo, Tohru Sawada, J Nagayama, Atsushi Satoh,T Mori,Akihiro Hasegawa,Hiroyuki Kurata,Kazuo Sukegawa,Atsuhiro Tsukune, Shinjiro Yamaguchi,Masataka Kase,Takatoshi Futatsugi,S Satoh,Toshihiro Sugii

Washington, DC（2007）

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摘要

We present an aggressively-scaled high-performance and low-power bulk CMOS platform technology aiming at large-scale (multi-core) high-end use with 45-nm ground rule. By utilizing a high-epsilon offset spacer and FET specific multiple-stressors with highly enhanced strain, world competitive high performance NFET and PFET drive currents of 1.22/0.765 mA/mum at 100 nA/mum off-current, and 0.97/0.63 mA/mum at 10 nA/mum off-current at |Vd|= 1V, respectively, were obtained with minimizing layout dependence. This technology also offers a functional high density SRAM with a much smaller cell, i.e., 0.255 mum2. In addition, full- porous low-k (k = 2.25) BEOL integration lowers RC delay and reduces total circuit delay by 25% at the long wiring region compared to that of our previous technology.

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关键词

cmos logic circuits,cmos memory circuits,mosfet,sram chips,integrated circuit interconnections,low-k dielectric thin films,beol integration,fet specific multiple-stressors,nfet drive currents,pfet drive currents,rc delay,full-porous low-k interconnects,functional high density sram,high-epsilon offset spacer,low-power bulk cmos platform technology,size 45 nm,total circuit delay,ultra low-k beol technology

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