300GHz Transistor Performance in Production CMOS Technologies

State College, PA, USA(2006)

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摘要
CMOS technology scaling has resulted in a continuous improvement in RF performance of silicon MOSFETs. fT and fMAX in excess of 300GHz has been demonstrated in production CMOS nodes [1]. 400GHz fT for ultra-short channel MOSFET with LGATE of 10nm has also been reported [2]. CMOS based RF solutions are already mainstream for applications in the 1-10GHz regime and with the RF performance of these devices improving rapidly, CMOS technology has the potential to enable low-power mm-wave applications as well. This paper will review the design and performance of state-of-the-art RF MOSFETs. RF CMOS device design relies on leveraging digital FET design coupled with geometry optimization to maximize device performance. COnsidering a small signal device model with parasitic resistances, fT of the device can be expressed as, 1/2??fT=Cin/gm+Cin/gm(rs +rd)gd+(rs+rd)Cgd. Even in FETs with LGATE ~ 25nm, the parasitic resistances and gd have a minimal impact on fT. If parasitic capacitances can be kept to a minimum then, fT=gm/2??Cin. From this expression, it can be observed that in velocity saturated devices, fT ?? 1/LGATE. This direct dependence on channel length has been the driving force for fT scaling in the FETs. in state-of-the CMOS nodes, gm also benefits from carrier mobility enhancement techniques. Tensile stress in the channel induced by nitride liners and "stress-memorization" has resulted in as much as 30% improvement of gm in nFETs [3,4].
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关键词
geometry,cmos technology,design optimization,silicon,radio frequency
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