Defect analysis and a new fault model for multi-port SRAMs

San Francisco, CA, 2001, Pages 366-374.

Cited by: 9|Views0


Semiconductor memory failures depend on the behavior of its components. This paper deals with testing of defects occurring in the memory cells of a multi-port memory. We also consider the resistive shorts between word/bit lines of same and different ports of the memory. The memory is modeled at the transistor level and analyzed for electr...More



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