Efficient test data compression and decompression for system-on-a-chip using internal scan chains and Golomb coding

We present a data compression method and decompres- sion architecture for testing embeddedcores in a system-on- a-chip (SOC). The proposed approach makes effective use of Golomb coding and the internal scan chains of the core under test, and provides significantly better results than a recent compression method that uses Golomb coding and a separate cyclical scan register (CSR). The use of the inter- nal scan chain for decompression obviates the need for a CSR. In addition, the novel interleaving decompression ar- chitecture allows multiple cores in an SOC to be tested con- currently using a single ATE I/O channel. We demonstrate the effectiveness of the proposed approach by applying it to the ISCAS 89 benchmark circuits.