A 2.3 GSample/s 10-tap digital FIR filter for magnetic recording read channels

San Francisco, CA, USA(2001)

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摘要
A 6 b 10 tap 2.3 GSample/s distributed-arithmetic digital FIR filter uses footless dynamic logic with delayed reset for precharge. The 0.5 mm/sup 2/ filter, fabricated in 0.18 /spl mu/m CMOS, is operational from 1 V to 2 V power supply. At 2.3 GSample/s, the power is 680 mW, and at 1 GSample/s the power is 120 mW.
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关键词
cmos digital integrated circuits,fir filters,digital arithmetic,magnetic recording,0.18 micron,1 to 2 v,120 to 680 mw,6 bit,cmos ic,digital fir filter,distributed arithmetic,footless dynamic logic,read channel,dynamic logic,fir filter
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