RLC signal integrity analysis of high-speed global interconnects [CMOS]
San Francisco, CA, USA（2000）
摘要
Inductive and capacitive coupling effects for high-speed global interconnects are studied via simulation. The impact of inductive coupling on delay and noise is found to be comparable to capacitive effects in high-speed buses. The results indicate that current-return paths are not strictly bounded by wide VDD/GND lines, so that inductive coupling is only partially eliminated by using shield wires. Shielding strategies for noise- and delay-sensitive nets is proposed, considering worst-case switching patterns.
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关键词
cmos integrated circuits,delays,high-speed integrated circuits,integrated circuit interconnections,integrated circuit modelling,integrated circuit noise,wiring,rlc signal integrity analysis,capacitive coupling effects,current-return paths,delay,high-speed buses,high-speed global interconnects,inductive coupling effects,noise,shield wires,worst-case switching patterns,signal integrity
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