A modular 0.13 /spl mu/m bulk CMOS technology for high performance and low power applications

L K Han,S Biesemans,John E Heidenreich,K Houlihan,Calvin Lin,Vincent Mcgahay,T Schiml, Andrew G Schmidt,Uwe Schroeder, M Stetter,Clement Hsingjen Wann,D Warner, R Mahnkopf,B Chen

Honolulu, HI, USA（2000）

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摘要

A leading-edge 0.13 /spl mu/m generation CMOS technology is presented as a platform for systems on a chip (SOC) applications. A modular triple gate oxide process concept is introduced for the first time to allow the optimization of high performance devices, low leakage devices, and I/O devices independently. Process commonality is also achieved to support deep-trench based embedded DRAM. Seven levels of Cu interconnects integrated with low-k ILD have been developed. With mature KrF 248 nm lithography and optical enhancement techniques, aggressive design rules are achieved to meet the circuit density requirement. A 2.48 /spl mu/m/sup 2/ functional 6T-SRAM cell is demonstrated.

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关键词

cmos memory circuits,dram chips,sram chips,integrated circuit interconnections,integrated circuit technology,low-power electronics,0.13 micron,248 nm,6t-sram cell,cmos technology,cu multilevel interconnect,krf lithography,embedded dram,low power circuit,low-k interlevel dielectric,modular triple gate oxide,optical enhancement,system-on-a-chip,leakage current,power generation,system on a chip,low power electronics,design rules

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