Enabling Soi-Based Assembly Technology For Three-Dimensional (3d) Integrated Circuits (Ics)
Washington, DC(2005)
摘要
We present solutions to the key process technology challenges of three-dimensional (3D) integrated circuits (ICs) that enable creation of stacked device layers with the shortest distance between them, the highest interconnection density and extremely aggressive wafer-to-wafer alignment. To achieve this important 3D IC technology milestone, we optimized the layer transfer process to include a glass handle wafer, oxide fusion bonding, wafer bow compensation methods, and a single damascene patterning and metallization method for creation of high-aspect-ratio (6:1 < AR < 11:1) contacts between two stacked device layers.
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关键词
three dimensional,silicon on insulator,high aspect ratio
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