High performance 0.18 /spl mu/m SOI CMOS technology

Effendi Leobandung,E Barth,M Sherony,S H Lo,R Schulz, W Chu,M Khare,Devendra K Sadana,Dominic J Schepis, R Boiam, I Sleight, F White,Fariborz Assaderaghi,D Moy, G A Biery,T C Chen,Bijan Davari,Ghavam G Shahidi

Washington, DC, USA（1999）

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摘要

A 0.18 /spl mu/m SOI CMOS technology is presented. Key features in this technology are: more aggressive gate lithography (equivalent to 0.15 /spl mu/m half pitch generation) and devices than previously reported 0.18 /spl mu/m CMOS technology, low dose SIMOX SOI substrate, dual gate oxide, low /spl epsi/ BEOL insulator, and 7 layer copper metalization. Inverter delay of less than 6.5 ps has been achieved with this technology. A POWER4/sup TM/ test chip was built using the 0.18 /spl mu/m SOI technology and has demonstrated performance above 1 GHz.

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关键词

cmos digital integrated circuits,simox,delays,integrated circuit interconnections,integrated circuit metallisation,integrated circuit testing,isolation technology,photolithography,0.18 micron,beol insulator,power4,soi cmos technology,dual gate oxide,gate lithography,half pitch generation,inverter delay,low dose simox,metalization

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