A 0.18um Dual Gate (3.5nm/6.8nm) CMOS Technology with Copper Metallurgy for Logic, SRAM, and Analog Applications
B Agarwala, M Armacost,S Biesemans, Lloyd G Burrell,Bomy Chen, K Han, D Harmon,John E Heidenreich, K Holloway,Terence B Hook,Sahil K Kapur, T Kebede, D Kiesling, Pangryong Kim, G Matusiewicz, Joseph M Lukaitis, P Nguyen, N Prabhakara,Stewart E Rauch,Nivo Rovedo,Laxmikant V Saraf,James A Slinkman, Hao Tang,R Wong, Sally J Yankee, K H Allers, A Augustin,G Brase,E Demm, C Derby, G Friese, Frank Grellner,Erdem Kaltalioglu, Mark Hoinkis,C Lin, R Mahnkopf, Odin Prigge,T Schafbauer,T Schiml, K Schruefer,Srikant Srinivasan, M Stetter, G Unger, R G Zoeller Solid-State Device Research Conference, 1999. Proceeding of the 29th European（1999）
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threshold voltage,doping,copper,cmos technology,space technology,microelectronics
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