Design and development of 130nm ICs for a 720 Gb/s networking system

Ajmal Khan,Kamalesh N Ruparel, C Joly, V Ghanta, Dat Le,T Nguyen, Songping Yang,Ishtiaq Ahmed, N Burnside,Man Hon Cheung,F Chiu,Yiping Fan, Dasong Ge, J S Gill, Peiyu Huang, V Jayapal, Oleksiy Kim, Meng Li, S Nguyen,P Tran,Hiep Truong,A Tsou, Dongping Wang, Xiaoyong Zhong

ieee（2005）

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摘要

A system-centric, fully-hierarchical design methodology and design techniques developed to create four ICs, which provide the core functionality of a multi-gigabit switching network system, are presented. The system is capable of switching more than 500 million packets per second. Electrical and physical design methods for one IC are described. ∼76M transistors are integrated in a 130nm CMOS 8-metal process. Functional and electrical design requirements were achieved with the first silicon.

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关键词

cmos integrated circuits,integrated circuit design,switching networks,system-on-chip,130 nm,720 gbit/s,cmos process,design validation,electrical design method,multigigabit switching network system,networking ic design,physical design method,power distribution,signal integrity,control systems,physical design,throughput,packet switching,design methodology,system on chip,engines,packaging

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