CVD Cu process integration for sub-0.25 μm technologies

San Francisco, CA(1998)

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摘要
This paper discusses CVD Cu process development and back-end dual-inlaid integration of CVD Cu on sub-0.25 μm device structure. CVD Cu was deposited on a variety of barriers, including CVD TiN, PVD Ta, PVD TaN and a hybrid barrier, using a direct liquid delivery (DLI) system. Excellent step coverage and via/trench filling were observed. Low sheet resistivity and low contact resistance have been obtained through a CVD/PVD reflow process using CVD TiN and hybrid barriers. The extendability of the CVD Cu based process technology is also discussed
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关键词
chemical interdiffusion,chemical vapour deposition,contact resistance,copper,diffusion barriers,electrical resistivity,integrated circuit interconnections,integrated circuit metallisation,integrated circuit testing,0.25 micron,cvd cu,cvd cu based process technology,cvd cu process development,cvd cu process integration,cvd tin barrier,cvd/pvd reflow process,cu,cu-ta,cu-tan,cu-tin,dli direct liquid delivery system,pvd ta barrier,pvd tan barrier,ta,tan,tin,back-end dual-inlaid integration,barrier layers,device structure,hybrid barrier,sheet resistivity,step coverage,trench filling,via filling,annealing,fluid flow,conductivity,etching,process integration,process development
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