Vertically-stacked on-chip SiGe/BiCMOS/RFCMOS coplanar waveguides

Wayne H Woods,Youri V Tretiakov,Kunal Vaed,David C Ahlgren,Jay Rascoe, R K Y Singh

ieee（2004）

引用 3|浏览3

暂无评分

摘要

This paper presents a new on-chip transmission line interconnect structure which offers the potential of superior return and insertion loss characteristics compared to the equivalent standard transmission line device. Conventional on-chip coplanar waveguides (CPW) and differential pairs are routed in a single metal layer in the chip's metal-dielectric stack. The vertically stacked coplanar waveguide (PW) transmission lines presented here consist of metal lines on multiple metal levels connected by continuous via bars. The additional cross-sectional area of the VCPW topology decreases interconnect resistance while the increased effective device thickness increases capacitance to neighboring ground return lines leading to a characteristics impedance reduction.

查看译文

关键词

bicmos integrated circuits,cmos integrated circuits,coplanar waveguides,integrated circuit interconnections,radiofrequency integrated circuits,transmission lines,bicmos,rfcmos,sige,vcpw topology,capacitance,device thickness,differential pair,ground return lines,impedance reduction,insertion loss characteristics,interconnect resistance,metal levels,metal lines,metal-dielectric stack,on-chip coplanar waveguides,on-chip transmission line interconnect structure,transmission line device,vertically-stacked interconnect,via bars,transmission line,coplanar waveguide,chip,topology,insertion loss,cross sectional area

AI 理解论文

溯源树

样例

生成溯源树，研究论文发展脉络

Chat Paper

正在生成论文摘要