Model-based guidelines to suppress cable discharge event (CDE) induced latchup in CMOS ICs

Kiran V Chatty,P E Cottrell,Robert J Gauthier,Mujahid Muhammad,Franco Stellari,Alan J Weger,Peilin Song,Moyra K Mcmanus

ieee（2004）

引用 41|浏览2

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摘要

An analytical model has been developed to provide physical design guidelines to suppress CDE-induced latchup in CMOS ICs. The design guidelines implemented in two test chips in IBM's 130nm technology successfully suppressed latchup against transient pulses of up to 6A peak current and against DC current pulses (EIA/JESD 78 test) of +/- 400mA.

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关键词

cmos integrated circuits,flip-flops,integrated circuit modelling,integrated circuit reliability,130 nm,6 a,cmos ics,dc current pulses,model-based guidelines,analytical model,physical design guidelines,suppress cable discharge event induced latchup,test chips,transient pulses,cmos technology,semiconductor device modeling,diodes,physical design,chip

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