A 9/spl mu/W 50MHz 32b adder using a self-adjusted forward body bias in SoCs

Ishibashi, K.,Yamashita, T., Arima, Y., Minematsu, I.

San Francisco, CA, USA（2003）

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摘要

This 32b adder in a 0.13/spl mu/m CMOS process consumes 9/spl mu/W at 50MHz and 0.3V and operates at 500MHz at 0.6V. Forward body biases are self-adjusted to minimize the threshold voltage and reduce PVT dependence. The power of the SoC can be reduced to 1/4 that of standard CMOS by gating the forward body bias in the IP blocks.

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关键词

CMOS logic circuits,adders,low-power electronics,system-on-chip,0.13 micron,0.3 V,0.6 V,32 bit,50 MHz,500 MHz,9 muW,CMOS process,IP block,PVT dependence,adder,low-power system-on-chip,self-adjusted forward body bias,threshold voltage,

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