3-dimensional vertical parallel plate capacitors in an SOI CMOS technology for integrated RF circuits

Jonghae Kim,J O Plouchart,N Zamdmer,M Sherony,Lianghung Lu,Yue Tan,M Yoon,K A Jenkins,M Kumar,A K Ray,L F Wagner

Kyoto, Japan（2003）

引用 42|浏览48

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摘要

This paper presents high-Q and high-density 3-dimensional VPP (vertical parallel plate) capacitors fabricated in a 0.12 /spl mu/m SOI CMOS technology. An effective capacitance density of 1.76 fF//spl mu/m/sup 2/ is obtained. A quality-factor of 22 at 1 GHz is obtained for a 20 pF VPP capacitor. Also, a VPP capacitor model is proposed for the first time to design the VPP capacitor.

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关键词

cmos integrated circuits,mim devices,uhf devices,capacitors,radiofrequency integrated circuits,silicon-on-insulator,0.12 micron,1 ghz,20 pf,3-dimensional vertical parallel plate capacitors,soi cmos technology,capacitance density,integrated radio frequency circuits,cmos technology,3 dimensional,geometry,radio frequency,quality factor,capacitance,silicon on insulator,conductivity

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