High performance 0.25 mu m p-MOSFETs with silicon-germanium channels for 300 K and 77 K operation

Washington, DC, USA, 1991, Pages 25-28.

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Abstract:

Quarter-micron Si/sub 1-x/Ge/sub x/ p-MOS devices with either thermal or PECVD oxides have been fabricated using an integrable process module (LOCOS isolation, threshold and deep well implants, p/sup +/ polysilicon gates, and TiSi/sub 2/) compatible with conventional 0.25 mu m CMOS with the Si/sub 1-x/Ge/sub x/ channel and Si cap deposite...More

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